Semiconductor chips with integrated circuits can be stacked, and terminals of the integrated circuits can be electrically connected. Through-silicon vias (TSVs) provide electric connections penetrating a silicon substrate of a chip.
U.S. Pat. No. 9,287,140 B2 discloses semiconductor packages. A plurality of semiconductor chips are stacked on a further semiconductor chip and bonded in a flip-chip manner to form a chip-on-wafer structure. The chips comprise a semiconductor substrate, integrated memory and logic circuits and through electrodes. A mold layer is formed to cover the chips and to provide rigidity to the further chip. The substrate of the further chip is thinned from its rear surface.
Y. Takahashi et al., “Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)”, Transactions of The Japan Institute of Electronics Packaging 5, 122-131 (2012) describe a package wherein a top die with micro-bumps is attached directly to the exposed TSV tips of a thin wafer-level chip scale package. Different under-fill properties, mold compound properties and mold techniques are evaluated.
F. Schrank et al., “Manufacturing of 3D-integrated Optoelectronic and Photonic ICs and Systems”, 45th European Solid State Device Research Conference 2015, describe sensor integration options including 3D integration concepts.